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Rev Log message Author Age Path
355 Import Julius Baxter's verilator hints from ORPSoC olof 4444d 02h /ethmac/
354 Whitespace cleanup olof 4444d 03h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 4446d 04h /ethmac/
352 Removed delayed assignments from rtl code olof 4450d 10h /ethmac/
351 Turn defines into parameters in eth_cop olof 4459d 00h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4459d 01h /ethmac/
349 Make all parameters configurable from top level olof 4460d 01h /ethmac/
348 Added option to dump VCD files olof 4461d 00h /ethmac/
347 Added information about running with Icarus Verilog olof 4461d 01h /ethmac/
346 Updated project location olof 4461d 03h /ethmac/
345 Temporarily disable failing tests olof 4461d 05h /ethmac/
344 bit 9 in phy control register is self clearing olof 4467d 07h /ethmac/
343 Address miss should not be asserted on short frames olof 4471d 03h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 4471d 03h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4471d 03h /ethmac/
340 Don't fail if log dir already exists olof 4472d 00h /ethmac/
339 Added basic support for Icarus Verilog olof 4473d 00h /ethmac/
338 root 5265d 05h /ethmac/
337 root 5321d 07h /ethernet/
336 Added old uploaded documents to new repository. root 5322d 11h /ethernet/

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