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Rev Log message Author Age Path
355 Import Julius Baxter's verilator hints from ORPSoC olof 3776d 09h /ethmac/
354 Whitespace cleanup olof 3776d 10h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 3778d 11h /ethmac/
352 Removed delayed assignments from rtl code olof 3782d 17h /ethmac/
351 Turn defines into parameters in eth_cop olof 3791d 07h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3791d 07h /ethmac/
349 Make all parameters configurable from top level olof 3792d 08h /ethmac/
348 Added option to dump VCD files olof 3793d 07h /ethmac/
347 Added information about running with Icarus Verilog olof 3793d 08h /ethmac/
346 Updated project location olof 3793d 10h /ethmac/
345 Temporarily disable failing tests olof 3793d 11h /ethmac/
344 bit 9 in phy control register is self clearing olof 3799d 13h /ethmac/
343 Address miss should not be asserted on short frames olof 3803d 09h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 3803d 09h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3803d 10h /ethmac/
340 Don't fail if log dir already exists olof 3804d 07h /ethmac/
339 Added basic support for Icarus Verilog olof 3805d 06h /ethmac/
338 root 4597d 12h /ethmac/
337 root 4653d 14h /ethernet/
336 Added old uploaded documents to new repository. root 4654d 17h /ethernet/

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