OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] - Rev 356

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4032d 04h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4032d 05h /ethmac/
354 Whitespace cleanup olof 4032d 05h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 4034d 07h /ethmac/
352 Removed delayed assignments from rtl code olof 4038d 13h /ethmac/
351 Turn defines into parameters in eth_cop olof 4047d 03h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4047d 03h /ethmac/
349 Make all parameters configurable from top level olof 4048d 04h /ethmac/
348 Added option to dump VCD files olof 4049d 03h /ethmac/
347 Added information about running with Icarus Verilog olof 4049d 03h /ethmac/
346 Updated project location olof 4049d 06h /ethmac/
345 Temporarily disable failing tests olof 4049d 07h /ethmac/
344 bit 9 in phy control register is self clearing olof 4055d 09h /ethmac/
343 Address miss should not be asserted on short frames olof 4059d 05h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 4059d 05h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4059d 05h /ethmac/
340 Don't fail if log dir already exists olof 4060d 03h /ethmac/
339 Added basic support for Icarus Verilog olof 4061d 02h /ethmac/
338 root 4853d 08h /ethmac/
337 root 4909d 10h /ethernet/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.