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Rev Log message Author Age Path
359 Verilator linting fixes olof 4675d 04h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4676d 18h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4676d 18h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4676d 20h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4676d 21h /ethmac/
354 Whitespace cleanup olof 4676d 21h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 4678d 23h /ethmac/
352 Removed delayed assignments from rtl code olof 4683d 05h /ethmac/
351 Turn defines into parameters in eth_cop olof 4691d 19h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4691d 19h /ethmac/
349 Make all parameters configurable from top level olof 4692d 20h /ethmac/
348 Added option to dump VCD files olof 4693d 19h /ethmac/
347 Added information about running with Icarus Verilog olof 4693d 20h /ethmac/
346 Updated project location olof 4693d 22h /ethmac/
345 Temporarily disable failing tests olof 4693d 23h /ethmac/
344 bit 9 in phy control register is self clearing olof 4700d 01h /ethmac/
343 Address miss should not be asserted on short frames olof 4703d 21h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 4703d 21h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4703d 22h /ethmac/
340 Don't fail if log dir already exists olof 4704d 19h /ethmac/

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