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Rev Log message Author Age Path
359 Verilator linting fixes olof 5209d 19h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 5211d 09h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 5211d 10h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 5211d 11h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 5211d 12h /ethmac/
354 Whitespace cleanup olof 5211d 13h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 5213d 14h /ethmac/
352 Removed delayed assignments from rtl code olof 5217d 20h /ethmac/
351 Turn defines into parameters in eth_cop olof 5226d 10h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 5226d 10h /ethmac/
349 Make all parameters configurable from top level olof 5227d 11h /ethmac/
348 Added option to dump VCD files olof 5228d 10h /ethmac/
347 Added information about running with Icarus Verilog olof 5228d 11h /ethmac/
346 Updated project location olof 5228d 13h /ethmac/
345 Temporarily disable failing tests olof 5228d 14h /ethmac/
344 bit 9 in phy control register is self clearing olof 5234d 16h /ethmac/
343 Address miss should not be asserted on short frames olof 5238d 12h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 5238d 12h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 5238d 13h /ethmac/
340 Don't fail if log dir already exists olof 5239d 10h /ethmac/
339 Added basic support for Icarus Verilog olof 5240d 10h /ethmac/
338 root 6032d 15h /ethmac/
337 root 6088d 17h /ethernet/
336 Added old uploaded documents to new repository. root 6089d 20h /ethernet/
335 New directory structure. root 6089d 20h /ethernet/

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