OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] - Rev 360

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 4657d 06h /ethmac/
359 Verilator linting fixes olof 4659d 08h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4660d 22h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4660d 23h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4661d 00h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4661d 01h /ethmac/
354 Whitespace cleanup olof 4661d 02h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 4663d 03h /ethmac/
352 Removed delayed assignments from rtl code olof 4667d 09h /ethmac/
351 Turn defines into parameters in eth_cop olof 4675d 23h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4675d 23h /ethmac/
349 Make all parameters configurable from top level olof 4677d 00h /ethmac/
348 Added option to dump VCD files olof 4677d 23h /ethmac/
347 Added information about running with Icarus Verilog olof 4678d 00h /ethmac/
346 Updated project location olof 4678d 02h /ethmac/
345 Temporarily disable failing tests olof 4678d 03h /ethmac/
344 bit 9 in phy control register is self clearing olof 4684d 05h /ethmac/
343 Address miss should not be asserted on short frames olof 4688d 01h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 4688d 01h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4688d 02h /ethmac/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.