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Rev Log message Author Age Path
363 quartus project files unneback 4507d 01h /ethmac/
362 added Makefiles to build project unneback 4507d 01h /ethmac/
361 created branch unneback unneback 4507d 01h /ethmac/
360 Added partial implementation of the debug register from ORPSoC olof 4508d 00h /ethmac/
359 Verilator linting fixes olof 4510d 02h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4511d 16h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4511d 16h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4511d 18h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4511d 19h /ethmac/
354 Whitespace cleanup olof 4511d 19h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 4513d 21h /ethmac/
352 Removed delayed assignments from rtl code olof 4518d 03h /ethmac/
351 Turn defines into parameters in eth_cop olof 4526d 17h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4526d 17h /ethmac/
349 Make all parameters configurable from top level olof 4527d 18h /ethmac/
348 Added option to dump VCD files olof 4528d 17h /ethmac/
347 Added information about running with Icarus Verilog olof 4528d 17h /ethmac/
346 Updated project location olof 4528d 19h /ethmac/
345 Temporarily disable failing tests olof 4528d 21h /ethmac/
344 bit 9 in phy control register is self clearing olof 4534d 23h /ethmac/

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