Subversion Repositories ethmac

[/] [ethmac/] - Rev 368


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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 3178d 14h /ethmac/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3241d 12h /ethmac/
366 Readded eth_top.v with a deprecation warning olof 3365d 16h /ethmac/
365 Whitespace cleanup olof 3366d 15h /ethmac/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3367d 12h /ethmac/
363 quartus project files unneback 3367d 21h /ethmac/
362 added Makefiles to build project unneback 3367d 21h /ethmac/
361 created branch unneback unneback 3367d 21h /ethmac/
360 Added partial implementation of the debug register from ORPSoC olof 3368d 20h /ethmac/
359 Verilator linting fixes olof 3370d 22h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3372d 12h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3372d 12h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3372d 14h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 3372d 15h /ethmac/
354 Whitespace cleanup olof 3372d 15h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 3374d 17h /ethmac/
352 Removed delayed assignments from rtl code olof 3378d 23h /ethmac/
351 Turn defines into parameters in eth_cop olof 3387d 13h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3387d 13h /ethmac/
349 Make all parameters configurable from top level olof 3388d 14h /ethmac/
348 Added option to dump VCD files olof 3389d 13h /ethmac/
347 Added information about running with Icarus Verilog olof 3389d 13h /ethmac/
346 Updated project location olof 3389d 16h /ethmac/
345 Temporarily disable failing tests olof 3389d 17h /ethmac/
344 bit 9 in phy control register is self clearing olof 3395d 19h /ethmac/
343 Address miss should not be asserted on short frames olof 3399d 15h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 3399d 15h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3399d 15h /ethmac/
340 Don't fail if log dir already exists olof 3400d 13h /ethmac/
339 Added basic support for Icarus Verilog olof 3401d 12h /ethmac/

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