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[/] [ethmac/] - Rev 368

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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 3540d 23h /ethmac/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3603d 20h /ethmac/
366 Readded eth_top.v with a deprecation warning olof 3728d 00h /ethmac/
365 Whitespace cleanup olof 3728d 23h /ethmac/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3729d 21h /ethmac/
363 quartus project files unneback 3730d 05h /ethmac/
362 added Makefiles to build project unneback 3730d 06h /ethmac/
361 created branch unneback unneback 3730d 06h /ethmac/
360 Added partial implementation of the debug register from ORPSoC olof 3731d 04h /ethmac/
359 Verilator linting fixes olof 3733d 07h /ethmac/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3734d 21h /ethmac/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3734d 21h /ethmac/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3734d 23h /ethmac/
355 Import Julius Baxter's verilator hints from ORPSoC olof 3734d 23h /ethmac/
354 Whitespace cleanup olof 3735d 00h /ethmac/
353 Inherit fixes for bit width of constants from ORPSoC olof 3737d 01h /ethmac/
352 Removed delayed assignments from rtl code olof 3741d 07h /ethmac/
351 Turn defines into parameters in eth_cop olof 3749d 21h /ethmac/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3749d 22h /ethmac/
349 Make all parameters configurable from top level olof 3750d 22h /ethmac/
348 Added option to dump VCD files olof 3751d 21h /ethmac/
347 Added information about running with Icarus Verilog olof 3751d 22h /ethmac/
346 Updated project location olof 3752d 00h /ethmac/
345 Temporarily disable failing tests olof 3752d 01h /ethmac/
344 bit 9 in phy control register is self clearing olof 3758d 04h /ethmac/
343 Address miss should not be asserted on short frames olof 3761d 23h /ethmac/
342 Added cast to avoid inequality when comparing different data types olof 3762d 00h /ethmac/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3762d 00h /ethmac/
340 Don't fail if log dir already exists olof 3762d 21h /ethmac/
339 Added basic support for Icarus Verilog olof 3763d 21h /ethmac/

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