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Rev Log message Author Age Path
232 fpga define added. mohor 7874d 00h /ethmac/branches/unneback/
231 Description of Core Modules added (figure). mohor 7876d 01h /ethmac/branches/unneback/
229 case changed to casex. mohor 7879d 22h /ethmac/branches/unneback/
227 Changed BIST scan signals. tadejm 7880d 02h /ethmac/branches/unneback/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7880d 03h /ethmac/branches/unneback/
225 Some minor changes. tadejm 7880d 03h /ethmac/branches/unneback/
224 Signals for a wave window in Modelsim. tadejm 7880d 04h /ethmac/branches/unneback/
223 Some code changed due to bug fixes. tadejm 7880d 05h /ethmac/branches/unneback/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7884d 03h /ethmac/branches/unneback/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7887d 03h /ethmac/branches/unneback/
218 Typo error fixed. (When using Bist) mohor 7887d 05h /ethmac/branches/unneback/
217 Bist supported. mohor 7887d 05h /ethmac/branches/unneback/
216 Bist signals added. mohor 7887d 05h /ethmac/branches/unneback/
215 Bist supported. mohor 7887d 06h /ethmac/branches/unneback/
214 Signals for WISHBONE B3 compliant interface added. mohor 7888d 02h /ethmac/branches/unneback/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7888d 02h /ethmac/branches/unneback/
212 Minor $display change. mohor 7888d 02h /ethmac/branches/unneback/
211 Bist added. mohor 7888d 02h /ethmac/branches/unneback/
210 BIST added. mohor 7888d 02h /ethmac/branches/unneback/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7889d 05h /ethmac/branches/unneback/

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