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Rev Log message Author Age Path
361 created branch unneback unneback 4668d 19h /ethmac/branches/unneback/bench/verilog/
348 Added option to dump VCD files olof 4690d 11h /ethmac/branches/unneback/bench/verilog/
346 Updated project location olof 4690d 13h /ethmac/branches/unneback/bench/verilog/
345 Temporarily disable failing tests olof 4690d 15h /ethmac/branches/unneback/bench/verilog/
344 bit 9 in phy control register is self clearing olof 4696d 17h /ethmac/branches/unneback/bench/verilog/
343 Address miss should not be asserted on short frames olof 4700d 13h /ethmac/branches/unneback/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4700d 13h /ethmac/branches/unneback/bench/verilog/
338 root 5494d 16h /ethmac/branches/unneback/bench/verilog/
335 New directory structure. root 5551d 21h /ethmac/branches/unneback/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 6999d 23h /ethmac/branches/unneback/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7028d 18h /ethmac/branches/unneback/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7360d 15h /ethmac/branches/unneback/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7472d 18h /ethmac/branches/unneback/bench/verilog/
302 mbist signals updated according to newest convention markom 7521d 23h /ethmac/branches/unneback/bench/verilog/
299 Artisan RAMs added. mohor 7579d 19h /ethmac/branches/unneback/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7647d 19h /ethmac/branches/unneback/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7780d 15h /ethmac/branches/unneback/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7781d 17h /ethmac/branches/unneback/bench/verilog/
274 Backup version. Not fully working. tadejm 7789d 11h /ethmac/branches/unneback/bench/verilog/
267 Full duplex control frames tested. mohor 7845d 15h /ethmac/branches/unneback/bench/verilog/

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