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[/] [ethmac/] [branches/] [unneback/] [bench/] [verilog/] - Rev 363

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Rev Log message Author Age Path
361 created branch unneback unneback 4646d 05h /ethmac/branches/unneback/bench/verilog/
348 Added option to dump VCD files olof 4667d 20h /ethmac/branches/unneback/bench/verilog/
346 Updated project location olof 4667d 23h /ethmac/branches/unneback/bench/verilog/
345 Temporarily disable failing tests olof 4668d 00h /ethmac/branches/unneback/bench/verilog/
344 bit 9 in phy control register is self clearing olof 4674d 02h /ethmac/branches/unneback/bench/verilog/
343 Address miss should not be asserted on short frames olof 4677d 22h /ethmac/branches/unneback/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4677d 23h /ethmac/branches/unneback/bench/verilog/
338 root 5472d 01h /ethmac/branches/unneback/bench/verilog/
335 New directory structure. root 5529d 06h /ethmac/branches/unneback/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 6977d 09h /ethmac/branches/unneback/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7006d 03h /ethmac/branches/unneback/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7338d 01h /ethmac/branches/unneback/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7450d 04h /ethmac/branches/unneback/bench/verilog/
302 mbist signals updated according to newest convention markom 7499d 09h /ethmac/branches/unneback/bench/verilog/
299 Artisan RAMs added. mohor 7557d 04h /ethmac/branches/unneback/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7625d 05h /ethmac/branches/unneback/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7758d 01h /ethmac/branches/unneback/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7759d 03h /ethmac/branches/unneback/bench/verilog/
274 Backup version. Not fully working. tadejm 7766d 21h /ethmac/branches/unneback/bench/verilog/
267 Full duplex control frames tested. mohor 7823d 00h /ethmac/branches/unneback/bench/verilog/
266 Flow control test almost finished. mohor 7827d 23h /ethmac/branches/unneback/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7828d 14h /ethmac/branches/unneback/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7829d 03h /ethmac/branches/unneback/bench/verilog/
254 Temp version. mohor 7830d 20h /ethmac/branches/unneback/bench/verilog/
252 Just some updates. tadejm 7830d 23h /ethmac/branches/unneback/bench/verilog/
243 Late collision is not reported any more. tadejm 7836d 03h /ethmac/branches/unneback/bench/verilog/
227 Changed BIST scan signals. tadejm 7862d 23h /ethmac/branches/unneback/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7863d 03h /ethmac/branches/unneback/bench/verilog/
216 Bist signals added. mohor 7870d 03h /ethmac/branches/unneback/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7872d 03h /ethmac/branches/unneback/bench/verilog/

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