URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 213

Rev	Log message	Author	Age	Path
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7928d 00h	/ethmac/branches/unneback/rtl/verilog/
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	7944d 03h	/ethmac/branches/unneback/rtl/verilog/
141	Syntax error fixed.	mohor	7946d 20h	/ethmac/branches/unneback/rtl/verilog/
140	Syntax error fixed.	mohor	7946d 20h	/ethmac/branches/unneback/rtl/verilog/
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	7946d 21h	/ethmac/branches/unneback/rtl/verilog/
138	Synchronous reset added.	mohor	7946d 21h	/ethmac/branches/unneback/rtl/verilog/
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7946d 21h	/ethmac/branches/unneback/rtl/verilog/
136	Parameter ResetValue changed to capital letters.	mohor	7947d 06h	/ethmac/branches/unneback/rtl/verilog/
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7948d 23h	/ethmac/branches/unneback/rtl/verilog/
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7949d 00h	/ethmac/branches/unneback/rtl/verilog/