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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 278

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Rev Log message Author Age Path
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7762d 01h /ethmac/branches/unneback/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7762d 02h /ethmac/branches/unneback/rtl/verilog/
276 Defer indication changed. tadejm 7762d 02h /ethmac/branches/unneback/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7769d 06h /ethmac/branches/unneback/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7770d 01h /ethmac/branches/unneback/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7771d 03h /ethmac/branches/unneback/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7772d 03h /ethmac/branches/unneback/rtl/verilog/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7831d 02h /ethmac/branches/unneback/rtl/verilog/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7831d 13h /ethmac/branches/unneback/rtl/verilog/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7832d 15h /ethmac/branches/unneback/rtl/verilog/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7832d 15h /ethmac/branches/unneback/rtl/verilog/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7832d 15h /ethmac/branches/unneback/rtl/verilog/
255 TPauseRq synchronized to tx_clk. mohor 7832d 15h /ethmac/branches/unneback/rtl/verilog/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7833d 21h /ethmac/branches/unneback/rtl/verilog/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7833d 21h /ethmac/branches/unneback/rtl/verilog/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7833d 21h /ethmac/branches/unneback/rtl/verilog/
248 wb_rst_i is used for MIIM reset. mohor 7834d 22h /ethmac/branches/unneback/rtl/verilog/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7838d 01h /ethmac/branches/unneback/rtl/verilog/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7838d 20h /ethmac/branches/unneback/rtl/verilog/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7839d 17h /ethmac/branches/unneback/rtl/verilog/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7839d 17h /ethmac/branches/unneback/rtl/verilog/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7839d 17h /ethmac/branches/unneback/rtl/verilog/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7839d 17h /ethmac/branches/unneback/rtl/verilog/
238 Defines fixed to use generic RAM by default. mohor 7851d 21h /ethmac/branches/unneback/rtl/verilog/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7854d 02h /ethmac/branches/unneback/rtl/verilog/
232 fpga define added. mohor 7859d 20h /ethmac/branches/unneback/rtl/verilog/
229 case changed to casex. mohor 7865d 18h /ethmac/branches/unneback/rtl/verilog/
227 Changed BIST scan signals. tadejm 7865d 22h /ethmac/branches/unneback/rtl/verilog/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7865d 23h /ethmac/branches/unneback/rtl/verilog/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7869d 23h /ethmac/branches/unneback/rtl/verilog/

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