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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 280

Rev	Log message	Author	Age	Path
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7836d 11h	/ethmac/branches/unneback/rtl/verilog/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7836d 11h	/ethmac/branches/unneback/rtl/verilog/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7836d 11h	/ethmac/branches/unneback/rtl/verilog/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7836d 11h	/ethmac/branches/unneback/rtl/verilog/
238	Defines fixed to use generic RAM by default.	mohor	7848d 15h	/ethmac/branches/unneback/rtl/verilog/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7850d 21h	/ethmac/branches/unneback/rtl/verilog/
232	fpga define added.	mohor	7856d 15h	/ethmac/branches/unneback/rtl/verilog/
229	case changed to casex.	mohor	7862d 13h	/ethmac/branches/unneback/rtl/verilog/
227	Changed BIST scan signals.	tadejm	7862d 17h	/ethmac/branches/unneback/rtl/verilog/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7862d 18h	/ethmac/branches/unneback/rtl/verilog/