OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 332

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7665d 03h /ethmac/branches/unneback/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7692d 21h /ethmac/branches/unneback/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7770d 22h /ethmac/branches/unneback/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7771d 00h /ethmac/branches/unneback/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7771d 00h /ethmac/branches/unneback/rtl/verilog/
276 Defer indication changed. tadejm 7771d 00h /ethmac/branches/unneback/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7778d 04h /ethmac/branches/unneback/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7778d 23h /ethmac/branches/unneback/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7780d 01h /ethmac/branches/unneback/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7781d 01h /ethmac/branches/unneback/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.