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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 341

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Rev	Log message	Author	Age	Path
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4677d 15h	/ethmac/branches/unneback/rtl/verilog/
338		root	5471d 18h	/ethmac/branches/unneback/rtl/verilog/
335	New directory structure.	root	5528d 23h	/ethmac/branches/unneback/rtl/verilog/
333	Some small fixes + some troubles fixed.	igorm	6977d 13h	/ethmac/branches/unneback/rtl/verilog/
332	Case statement improved for synthesys.	igorm	6990d 18h	/ethmac/branches/unneback/rtl/verilog/
330	Warning fixes.	igorm	7005d 20h	/ethmac/branches/unneback/rtl/verilog/
329	Defer indication fixed.	igorm	7005d 21h	/ethmac/branches/unneback/rtl/verilog/
328	Delayed CRC fixed.	igorm	7005d 22h	/ethmac/branches/unneback/rtl/verilog/
327	Defer indication fixed.	igorm	7005d 22h	/ethmac/branches/unneback/rtl/verilog/
326	Delayed CRC fixed.	igorm	7005d 22h	/ethmac/branches/unneback/rtl/verilog/
325	Defer indication fixed.	igorm	7005d 22h	/ethmac/branches/unneback/rtl/verilog/
323	Accidently deleted line put back.	igorm	7302d 22h	/ethmac/branches/unneback/rtl/verilog/
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7306d 17h	/ethmac/branches/unneback/rtl/verilog/
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7306d 21h	/ethmac/branches/unneback/rtl/verilog/
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7346d 23h	/ethmac/branches/unneback/rtl/verilog/
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7449d 20h	/ethmac/branches/unneback/rtl/verilog/
306	Lapsus fixed (!we -> ~we).	simons	7450d 18h	/ethmac/branches/unneback/rtl/verilog/
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7472d 15h	/ethmac/branches/unneback/rtl/verilog/
302	mbist signals updated according to newest convention	markom	7499d 01h	/ethmac/branches/unneback/rtl/verilog/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7509d 17h	/ethmac/branches/unneback/rtl/verilog/

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 341

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