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Rev Log message Author Age Path
297 Artisan ram instance added. simons 7732d 22h /ethmac/branches/unneback/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 7769d 00h /ethmac/branches/unneback/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7795d 03h /ethmac/branches/unneback/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 7795d 03h /ethmac/branches/unneback/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7823d 05h /ethmac/branches/unneback/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7850d 22h /ethmac/branches/unneback/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7929d 00h /ethmac/branches/unneback/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7929d 01h /ethmac/branches/unneback/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7929d 01h /ethmac/branches/unneback/rtl/verilog/
276 Defer indication changed. tadejm 7929d 01h /ethmac/branches/unneback/rtl/verilog/

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