URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 350

Rev	Log message	Author	Age	Path
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7483d 08h	/ethmac/branches/unneback/rtl/verilog/
302	mbist signals updated according to newest convention	markom	7509d 19h	/ethmac/branches/unneback/rtl/verilog/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7520d 11h	/ethmac/branches/unneback/rtl/verilog/
297	Artisan ram instance added.	simons	7573d 10h	/ethmac/branches/unneback/rtl/verilog/
288	This file was not part of the RTL before, but it should be here.	simons	7609d 12h	/ethmac/branches/unneback/rtl/verilog/
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7635d 15h	/ethmac/branches/unneback/rtl/verilog/
285	Binary operator used instead of unary (xnor).	mohor	7635d 15h	/ethmac/branches/unneback/rtl/verilog/
284	Busy was set 2 cycles too late. Reported by Dennis Scott.	mohor	7663d 16h	/ethmac/branches/unneback/rtl/verilog/
283	RxBDAddress was updated also when value to r_TxBDNum was written with greater value than allowed.	mohor	7691d 10h	/ethmac/branches/unneback/rtl/verilog/
280	Reset has priority in some flipflops.	mohor	7769d 12h	/ethmac/branches/unneback/rtl/verilog/