URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 362

Rev	Log message	Author	Age	Path
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7326d 14h	/ethmac/branches/unneback/rtl/verilog
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7366d 17h	/ethmac/branches/unneback/rtl/verilog
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7469d 13h	/ethmac/branches/unneback/rtl/verilog
306	Lapsus fixed (!we -> ~we).	simons	7470d 11h	/ethmac/branches/unneback/rtl/verilog
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7492d 08h	/ethmac/branches/unneback/rtl/verilog
302	mbist signals updated according to newest convention	markom	7518d 18h	/ethmac/branches/unneback/rtl/verilog
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7529d 10h	/ethmac/branches/unneback/rtl/verilog
297	Artisan ram instance added.	simons	7582d 09h	/ethmac/branches/unneback/rtl/verilog
288	This file was not part of the RTL before, but it should be here.	simons	7618d 11h	/ethmac/branches/unneback/rtl/verilog
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7644d 14h	/ethmac/branches/unneback/rtl/verilog