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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 363

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Rev Log message Author Age Path
363 quartus project files unneback 4729d 15h /ethmac/branches/unneback/rtl/verilog/
362 added Makefiles to build project unneback 4729d 15h /ethmac/branches/unneback/rtl/verilog/
361 created branch unneback unneback 4729d 15h /ethmac/branches/unneback/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4740d 17h /ethmac/branches/unneback/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4749d 06h /ethmac/branches/unneback/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4749d 07h /ethmac/branches/unneback/rtl/verilog/
349 Make all parameters configurable from top level olof 4750d 08h /ethmac/branches/unneback/rtl/verilog/
346 Updated project location olof 4751d 09h /ethmac/branches/unneback/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4761d 09h /ethmac/branches/unneback/rtl/verilog/
338 root 5555d 12h /ethmac/branches/unneback/rtl/verilog/
335 New directory structure. root 5612d 17h /ethmac/branches/unneback/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7061d 07h /ethmac/branches/unneback/rtl/verilog/
332 Case statement improved for synthesys. igorm 7074d 12h /ethmac/branches/unneback/rtl/verilog/
330 Warning fixes. igorm 7089d 14h /ethmac/branches/unneback/rtl/verilog/
329 Defer indication fixed. igorm 7089d 15h /ethmac/branches/unneback/rtl/verilog/
328 Delayed CRC fixed. igorm 7089d 16h /ethmac/branches/unneback/rtl/verilog/
327 Defer indication fixed. igorm 7089d 16h /ethmac/branches/unneback/rtl/verilog/
326 Delayed CRC fixed. igorm 7089d 16h /ethmac/branches/unneback/rtl/verilog/
325 Defer indication fixed. igorm 7089d 16h /ethmac/branches/unneback/rtl/verilog/
323 Accidently deleted line put back. igorm 7386d 16h /ethmac/branches/unneback/rtl/verilog/

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