OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_defines.v] - Rev 361

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
361 created branch unneback unneback 4835d 06h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
351 Turn defines into parameters in eth_cop olof 4854d 22h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4854d 22h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
346 Updated project location olof 4857d 01h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
338 root 5661d 03h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
335 New directory structure. root 5718d 08h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
330 Warning fixes. igorm 7195d 05h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7662d 00h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
302 mbist signals updated according to newest convention markom 7688d 10h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
297 Artisan ram instance added. simons 7752d 01h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7814d 06h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 8020d 00h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 8024d 04h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 8038d 00h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
232 fpga define added. mohor 8045d 23h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 8060d 01h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
211 Bist added. mohor 8060d 02h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 8077d 00h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 8096d 00h /ethmac/branches/unneback/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 8114d 20h /ethmac/branches/unneback/rtl/verilog/eth_defines.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.