OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_fifo.v] - Rev 362

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
361 created branch unneback unneback 3397d 20h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
352 Removed delayed assignments from rtl code olof 3408d 21h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
346 Updated project location olof 3419d 14h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
338 root 4223d 16h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
335 New directory structure. root 4280d 22h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
330 Warning fixes. igorm 5757d 19h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6793d 18h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 6821d 18h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 6869d 15h /ethmac/branches/unneback/rtl/verilog/eth_fifo.v

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.