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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_macstatus.v] - Rev 361

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361 created branch unneback unneback 4653d 10h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
352 Removed delayed assignments from rtl code olof 4664d 12h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
346 Updated project location olof 4675d 05h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
338 root 5479d 07h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
335 New directory structure. root 5536d 12h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
333 Some small fixes + some troubles fixed. igorm 6985d 02h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
325 Defer indication fixed. igorm 7013d 12h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
276 Defer indication changed. tadejm 7766d 09h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7835d 20h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7844d 00h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7906d 07h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7914d 04h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
126 InvalidSymbol generation changed. mohor 7955d 04h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8049d 08h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
70 Small fixes. mohor 8112d 12h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8115d 05h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
43 Tx status is written back to the BD. mohor 8119d 13h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
42 Rx status is written back to the BD. mohor 8122d 06h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
37 Link in the header changed. mohor 8138d 12h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8234d 13h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
18 Few little NCSIM warnings fixed. mohor 8272d 08h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8308d 07h /ethmac/branches/unneback/rtl/verilog/eth_macstatus.v

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