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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_registers.v] - Rev 352

Rev	Log message	Author	Age	Path
74	Reset values are passed to registers through parameters	mohor	8118d 12h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
69	Define missmatch fixed.	mohor	8127d 15h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
68	Registered trimmed. Unused registers removed.	mohor	8128d 14h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
56	File format fixed a bit.	mohor	8129d 17h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8130d 08h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
46	HASH0 and HASH1 registers added.	mohor	8132d 11h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
37	Link in the header changed.	mohor	8152d 18h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8201d 13h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8201d 18h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8248d 19h	/ethmac/branches/unneback/rtl/verilog/eth_registers.v