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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Rev 341

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Rev Log message Author Age Path
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4682d 06h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
338 root 5476d 09h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
335 New directory structure. root 5533d 14h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7832d 22h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7835d 06h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
148 Bug when last byte of destination address was not checked fixed. mohor 7911d 05h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8079d 09h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
85 Log info was missing. mohor 8097d 03h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
83 MAC address recognition was not correct (bytes swaped). mohor 8097d 03h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
75 r_Bro is used for accepting/denying frames mohor 8101d 08h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8111d 17h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v
50 checks destination address for Unicast, Multicast and Broadcast ops billditt 8113d 05h /ethmac/branches/unneback/rtl/verilog/eth_rxaddrcheck.v

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