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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_rxethmac.v] - Rev 341

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Rev	Log message	Author	Age	Path
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4683d 20h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
338		root	5477d 23h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
335	New directory structure.	root	5535d 04h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
330	Warning fixes.	igorm	7012d 01h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7312d 23h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7353d 05h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7834d 12h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7836d 21h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
65	Testbench fixed, code simplified, unused signals removed.	mohor	8113d 07h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
62	RxAbort is an output. No need to have is declared as wire.	mohor	8114d 00h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
58	File format changed.	mohor	8114d 03h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
53	Addition of new module eth_addrcheck.v	billditt	8114d 17h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
37	Link in the header changed.	mohor	8137d 04h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8233d 05h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
18	Few little NCSIM warnings fixed.	mohor	8271d 00h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8306d 23h	/ethmac/branches/unneback/rtl/verilog/eth_rxethmac.v

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