OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_shiftreg.v] - Rev 361

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
361 created branch unneback unneback 4872d 05h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
352 Removed delayed assignments from rtl code olof 4883d 06h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
346 Updated project location olof 4893d 23h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
338 root 5698d 01h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
335 New directory structure. root 5755d 07h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
332 Case statement improved for synthesys. igorm 7217d 02h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
131 LinkFail signal was not latching appropriate bit. mohor 8153d 22h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
84 LinkFail signal was not latching appropriate bit. mohor 8318d 19h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
37 Link in the header changed. mohor 8357d 06h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8453d 08h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8527d 02h /ethmac/branches/unneback/rtl/verilog/eth_shiftreg.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.