URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Rev 335

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
335	New directory structure.	root	5532d 13h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
333	Some small fixes + some troubles fixed.	igorm	6981d 03h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
327	Defer indication fixed.	igorm	7009d 12h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7310d 08h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7476d 05h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
302	mbist signals updated according to newest convention	markom	7502d 16h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7513d 08h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
276	Defer indication changed.	tadejm	7762d 10h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
272	When control packets were received, they were ignored in some cases.	tadejm	7770d 10h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7771d 11h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7831d 22h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
255	TPauseRq synchronized to tx_clk.	mohor	7832d 23h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7834d 05h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7834d 06h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
248	wb_rst_i is used for MIIM reset.	mohor	7835d 06h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7839d 05h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7840d 01h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
227	Changed BIST scan signals.	tadejm	7866d 06h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
218	Typo error fixed. (When using Bist)	mohor	7873d 10h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
214	Signals for WISHBONE B3 compliant interface added.	mohor	7874d 07h	/ethmac/branches/unneback/rtl/verilog/eth_top.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Rev 335

Filtering Options