URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7971d 10h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7973d 13h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7977d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7978d 13h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7986d 02h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7986d 16h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7987d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7987d 08h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8054d 19h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8063d 20h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8089d 13h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8093d 13h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8099d 16h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8099d 16h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8109d 13h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8109d 15h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8110d 22h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8116d 10h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8120d 12h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8120d 12h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

Filtering Options