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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 270

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270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7773d 22h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7774d 22h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7833d 21h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7834d 08h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7836d 17h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7842d 12h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 7868d 14h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 7868d 17h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7868d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7872d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7875d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 7876d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7905d 20h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7906d 21h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7907d 00h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7908d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7912d 16h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7933d 15h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7953d 16h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7955d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7959d 10h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7960d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7968d 08h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7968d 21h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7969d 11h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7969d 14h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8037d 00h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8046d 02h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8071d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8075d 18h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

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