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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 323

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166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7909d 01h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7909d 04h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7910d 22h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7914d 20h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7935d 19h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7955d 20h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7957d 23h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7961d 14h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7962d 23h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7970d 12h /ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

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