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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 362

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Rev	Log message	Author	Age	Path
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7980d 23h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	8007d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	8007d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	8007d 06h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	8011d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	8014d 06h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
210	BIST added.	mohor	8015d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	8044d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	8045d 08h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
164	Ethernet debug registers removed.	mohor	8045d 11h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

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