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[/] [ethmac/] [tags/] [asyst_2/] - Rev 221

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7890d 17h /ethmac/tags/asyst_2
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7893d 17h /ethmac/tags/asyst_2
218 Typo error fixed. (When using Bist) mohor 7893d 19h /ethmac/tags/asyst_2
217 Bist supported. mohor 7893d 19h /ethmac/tags/asyst_2
216 Bist signals added. mohor 7893d 19h /ethmac/tags/asyst_2
215 Bist supported. mohor 7893d 20h /ethmac/tags/asyst_2
214 Signals for WISHBONE B3 compliant interface added. mohor 7894d 16h /ethmac/tags/asyst_2
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7894d 16h /ethmac/tags/asyst_2
212 Minor $display change. mohor 7894d 16h /ethmac/tags/asyst_2
211 Bist added. mohor 7894d 16h /ethmac/tags/asyst_2
210 BIST added. mohor 7894d 16h /ethmac/tags/asyst_2
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7895d 19h /ethmac/tags/asyst_2
208 Virtual Silicon RAMs moved to lib directory tadej 7911d 13h /ethmac/tags/asyst_2
207 Virtual Silicon RAM support fixed tadej 7911d 13h /ethmac/tags/asyst_2
206 Virtual Silicon RAM added to the simulation. mohor 7911d 14h /ethmac/tags/asyst_2
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7911d 14h /ethmac/tags/asyst_2
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7911d 14h /ethmac/tags/asyst_2
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7911d 14h /ethmac/tags/asyst_2
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7914d 15h /ethmac/tags/asyst_2
201 Core size added to the document. mohor 7914d 16h /ethmac/tags/asyst_2

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