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[/] [ethmac/] [tags/] [asyst_2/] - Rev 252

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Rev Log message Author Age Path
252 Just some updates. tadejm 8000d 08h /ethmac/tags/asyst_2/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 8000d 09h /ethmac/tags/asyst_2/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 8000d 09h /ethmac/tags/asyst_2/
248 wb_rst_i is used for MIIM reset. mohor 8001d 09h /ethmac/tags/asyst_2/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 8004d 12h /ethmac/tags/asyst_2/
245 Rev 1.7. mohor 8005d 05h /ethmac/tags/asyst_2/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 8005d 08h /ethmac/tags/asyst_2/
243 Late collision is not reported any more. tadejm 8005d 13h /ethmac/tags/asyst_2/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 8006d 04h /ethmac/tags/asyst_2/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 8006d 04h /ethmac/tags/asyst_2/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 8006d 04h /ethmac/tags/asyst_2/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 8006d 04h /ethmac/tags/asyst_2/
238 Defines fixed to use generic RAM by default. mohor 8018d 08h /ethmac/tags/asyst_2/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 8020d 13h /ethmac/tags/asyst_2/
235 rev 4. mohor 8021d 04h /ethmac/tags/asyst_2/
234 Figure list assed to the revision 3. mohor 8021d 12h /ethmac/tags/asyst_2/
233 Revision 0.3 released. Some figures added. mohor 8021d 12h /ethmac/tags/asyst_2/
232 fpga define added. mohor 8026d 07h /ethmac/tags/asyst_2/
231 Description of Core Modules added (figure). mohor 8028d 09h /ethmac/tags/asyst_2/
229 case changed to casex. mohor 8032d 05h /ethmac/tags/asyst_2/
227 Changed BIST scan signals. tadejm 8032d 09h /ethmac/tags/asyst_2/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 8032d 10h /ethmac/tags/asyst_2/
225 Some minor changes. tadejm 8032d 11h /ethmac/tags/asyst_2/
224 Signals for a wave window in Modelsim. tadejm 8032d 12h /ethmac/tags/asyst_2/
223 Some code changed due to bug fixes. tadejm 8032d 12h /ethmac/tags/asyst_2/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 8036d 10h /ethmac/tags/asyst_2/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 8039d 11h /ethmac/tags/asyst_2/
218 Typo error fixed. (When using Bist) mohor 8039d 13h /ethmac/tags/asyst_2/
217 Bist supported. mohor 8039d 13h /ethmac/tags/asyst_2/
216 Bist signals added. mohor 8039d 13h /ethmac/tags/asyst_2/

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