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[/] [ethmac/] [tags/] [asyst_2/] [rtl/] - Rev 253

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253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7319d 14h /ethmac/tags/asyst_2/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7319d 14h /ethmac/tags/asyst_2/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7319d 14h /ethmac/tags/asyst_2/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7320d 14h /ethmac/tags/asyst_2/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7323d 17h /ethmac/tags/asyst_2/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7324d 13h /ethmac/tags/asyst_2/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7325d 09h /ethmac/tags/asyst_2/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7325d 09h /ethmac/tags/asyst_2/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7325d 09h /ethmac/tags/asyst_2/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7325d 09h /ethmac/tags/asyst_2/rtl/
238 Defines fixed to use generic RAM by default. mohor 7337d 13h /ethmac/tags/asyst_2/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7339d 19h /ethmac/tags/asyst_2/rtl/
232 fpga define added. mohor 7345d 13h /ethmac/tags/asyst_2/rtl/
229 case changed to casex. mohor 7351d 11h /ethmac/tags/asyst_2/rtl/
227 Changed BIST scan signals. tadejm 7351d 15h /ethmac/tags/asyst_2/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7351d 16h /ethmac/tags/asyst_2/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7355d 16h /ethmac/tags/asyst_2/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7358d 16h /ethmac/tags/asyst_2/rtl/
218 Typo error fixed. (When using Bist) mohor 7358d 18h /ethmac/tags/asyst_2/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7359d 15h /ethmac/tags/asyst_2/rtl/

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