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[/] [ethmac/] [tags/] [asyst_2/] [rtl/] [verilog/] [eth_defines.v] - Rev 338

Rev	Log message	Author	Age	Path
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8094d 23h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
73	Number of interrupts changed	mohor	8115d 20h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
68	Registered trimmed. Unused registers removed.	mohor	8125d 22h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8125d 23h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
55	Changed that were lost with last update put back to the file.	mohor	8127d 01h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8127d 16h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
46	HASH0 and HASH1 registers added.	mohor	8129d 19h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
42	Rx status is written back to the BD.	mohor	8133d 20h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8136d 20h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v
37	Link in the header changed.	mohor	8150d 02h	/ethmac/tags/asyst_2/rtl/verilog/eth_defines.v