URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [asyst_2/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
338		root	5469d 18h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
335	New directory structure.	root	5526d 23h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
313	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7447d 21h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7470d 15h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
302	mbist signals updated according to newest convention	markom	7497d 02h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
280	Reset has priority in some flipflops.	mohor	7756d 19h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7756d 20h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
272	When control packets were received, they were ignored in some cases.	tadejm	7764d 20h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7765d 21h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7766d 21h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7825d 20h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7826d 08h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7828d 16h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7834d 11h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7860d 13h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7860d 16h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7860d 18h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7864d 17h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7867d 18h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v
210	BIST added.	mohor	7868d 17h	/ethmac/tags/asyst_2/rtl/verilog/eth_wishbone.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [asyst_2/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

Filtering Options