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[/] [ethmac/] [tags/] [asyst_3/] [rtl/] - Rev 270

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Rev Log message Author Age Path
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7767d 06h /ethmac/tags/asyst_3/rtl/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7768d 06h /ethmac/tags/asyst_3/rtl/
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7827d 05h /ethmac/tags/asyst_3/rtl/
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7827d 16h /ethmac/tags/asyst_3/rtl/
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7828d 18h /ethmac/tags/asyst_3/rtl/
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7828d 18h /ethmac/tags/asyst_3/rtl/
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7828d 18h /ethmac/tags/asyst_3/rtl/
255 TPauseRq synchronized to tx_clk. mohor 7828d 18h /ethmac/tags/asyst_3/rtl/
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7830d 00h /ethmac/tags/asyst_3/rtl/
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7830d 01h /ethmac/tags/asyst_3/rtl/
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7830d 01h /ethmac/tags/asyst_3/rtl/
248 wb_rst_i is used for MIIM reset. mohor 7831d 01h /ethmac/tags/asyst_3/rtl/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7834d 04h /ethmac/tags/asyst_3/rtl/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7835d 00h /ethmac/tags/asyst_3/rtl/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7835d 20h /ethmac/tags/asyst_3/rtl/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7835d 20h /ethmac/tags/asyst_3/rtl/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7835d 20h /ethmac/tags/asyst_3/rtl/
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7835d 20h /ethmac/tags/asyst_3/rtl/
238 Defines fixed to use generic RAM by default. mohor 7848d 00h /ethmac/tags/asyst_3/rtl/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7850d 05h /ethmac/tags/asyst_3/rtl/
232 fpga define added. mohor 7855d 23h /ethmac/tags/asyst_3/rtl/
229 case changed to casex. mohor 7861d 21h /ethmac/tags/asyst_3/rtl/
227 Changed BIST scan signals. tadejm 7862d 01h /ethmac/tags/asyst_3/rtl/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7862d 03h /ethmac/tags/asyst_3/rtl/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7866d 02h /ethmac/tags/asyst_3/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7869d 03h /ethmac/tags/asyst_3/rtl/
218 Typo error fixed. (When using Bist) mohor 7869d 05h /ethmac/tags/asyst_3/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7870d 01h /ethmac/tags/asyst_3/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7870d 01h /ethmac/tags/asyst_3/rtl/
212 Minor $display change. mohor 7870d 01h /ethmac/tags/asyst_3/rtl/

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