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Rev Log message Author Age Path
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7472d 16h /ethmac/tags/rel_1/
99 Document revised. mohor 7479d 14h /ethmac/tags/rel_1/
98 Document revised. mohor 7479d 15h /ethmac/tags/rel_1/
97 Small typo fixed. lampret 7496d 13h /ethmac/tags/rel_1/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 7500d 13h /ethmac/tags/rel_1/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7500d 16h /ethmac/tags/rel_1/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7500d 16h /ethmac/tags/rel_1/
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 7505d 14h /ethmac/tags/rel_1/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 7506d 16h /ethmac/tags/rel_1/
91 Comments in Slovene language removed. mohor 7506d 17h /ethmac/tags/rel_1/
90 casex changed with case, fifo reset changed. mohor 7506d 17h /ethmac/tags/rel_1/
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
mohor 7510d 14h /ethmac/tags/rel_1/
88 rx_fifo was not always cleared ok. Fixed. mohor 7516d 13h /ethmac/tags/rel_1/
87 Status was not latched correctly sometimes. Fixed. mohor 7516d 16h /ethmac/tags/rel_1/
86 Big Endian problem when sending frames fixed. mohor 7517d 22h /ethmac/tags/rel_1/
85 Log info was missing. mohor 7523d 08h /ethmac/tags/rel_1/
84 LinkFail signal was not latching appropriate bit. mohor 7523d 08h /ethmac/tags/rel_1/
83 MAC address recognition was not correct (bytes swaped). mohor 7523d 08h /ethmac/tags/rel_1/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 7523d 10h /ethmac/tags/rel_1/
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 7523d 10h /ethmac/tags/rel_1/

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