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[/] [ethmac/] [tags/] [rel_1/] - Rev 117

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Rev Log message Author Age Path
117 Clock mrx_clk set to 2.5 MHz. mohor 7961d 18h /ethmac/tags/rel_1
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7961d 18h /ethmac/tags/rel_1
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7962d 15h /ethmac/tags/rel_1
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7963d 13h /ethmac/tags/rel_1
113 RxPointer bug fixed. mohor 7970d 05h /ethmac/tags/rel_1
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7970d 18h /ethmac/tags/rel_1
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7971d 08h /ethmac/tags/rel_1
110 m_wb_cyc_o signal released after every single transfer. mohor 7971d 11h /ethmac/tags/rel_1
109 Comment removed. mohor 7971d 11h /ethmac/tags/rel_1
108 Testbench supports unaligned accesses. mohor 8038d 21h /ethmac/tags/rel_1
107 TX_BUF_BASE changed. mohor 8038d 21h /ethmac/tags/rel_1
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8038d 21h /ethmac/tags/rel_1
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8047d 23h /ethmac/tags/rel_1
104 FCS should not be included in NibbleMinFl. mohor 8049d 17h /ethmac/tags/rel_1
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8049d 17h /ethmac/tags/rel_1
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8049d 18h /ethmac/tags/rel_1
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8049d 18h /ethmac/tags/rel_1
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8049d 18h /ethmac/tags/rel_1
99 Document revised. mohor 8056d 17h /ethmac/tags/rel_1
98 Document revised. mohor 8056d 17h /ethmac/tags/rel_1

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