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Rev Log message Author Age Path
338 root 5476d 05h /ethmac/tags/rel_1
335 New directory structure. root 5533d 10h /ethmac/tags/rel_1
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7954d 03h /ethmac/tags/rel_1
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7954d 03h /ethmac/tags/rel_1
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7954d 03h /ethmac/tags/rel_1
120 Unused files removed. mohor 7954d 04h /ethmac/tags/rel_1
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7954d 04h /ethmac/tags/rel_1
118 ShiftEnded synchronization changed. mohor 7957d 19h /ethmac/tags/rel_1
117 Clock mrx_clk set to 2.5 MHz. mohor 7958d 06h /ethmac/tags/rel_1
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7958d 06h /ethmac/tags/rel_1
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7959d 04h /ethmac/tags/rel_1
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7960d 01h /ethmac/tags/rel_1
113 RxPointer bug fixed. mohor 7966d 17h /ethmac/tags/rel_1
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7967d 07h /ethmac/tags/rel_1
111 Master state machine had a bug when switching from master write to
master read.
mohor 7967d 20h /ethmac/tags/rel_1
110 m_wb_cyc_o signal released after every single transfer. mohor 7967d 23h /ethmac/tags/rel_1
109 Comment removed. mohor 7968d 00h /ethmac/tags/rel_1
108 Testbench supports unaligned accesses. mohor 8035d 10h /ethmac/tags/rel_1
107 TX_BUF_BASE changed. mohor 8035d 10h /ethmac/tags/rel_1
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8035d 10h /ethmac/tags/rel_1

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