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[/] [ethmac/] [tags/] [rel_1/] [rtl/] - Rev 105

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Rev	Log message	Author	Age	Path
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8039d 13h	/ethmac/tags/rel_1/rtl
104	FCS should not be included in NibbleMinFl.	mohor	8041d 07h	/ethmac/tags/rel_1/rtl
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8041d 07h	/ethmac/tags/rel_1/rtl
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8041d 07h	/ethmac/tags/rel_1/rtl
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8041d 08h	/ethmac/tags/rel_1/rtl
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8041d 08h	/ethmac/tags/rel_1/rtl
97	Small typo fixed.	lampret	8065d 05h	/ethmac/tags/rel_1/rtl
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8069d 05h	/ethmac/tags/rel_1/rtl
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8069d 08h	/ethmac/tags/rel_1/rtl
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8069d 08h	/ethmac/tags/rel_1/rtl
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8074d 06h	/ethmac/tags/rel_1/rtl
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8075d 09h	/ethmac/tags/rel_1/rtl
91	Comments in Slovene language removed.	mohor	8075d 09h	/ethmac/tags/rel_1/rtl
90	casex changed with case, fifo reset changed.	mohor	8075d 09h	/ethmac/tags/rel_1/rtl
88	rx_fifo was not always cleared ok. Fixed.	mohor	8085d 05h	/ethmac/tags/rel_1/rtl
87	Status was not latched correctly sometimes. Fixed.	mohor	8085d 08h	/ethmac/tags/rel_1/rtl
86	Big Endian problem when sending frames fixed.	mohor	8086d 15h	/ethmac/tags/rel_1/rtl
85	Log info was missing.	mohor	8092d 00h	/ethmac/tags/rel_1/rtl
84	LinkFail signal was not latching appropriate bit.	mohor	8092d 00h	/ethmac/tags/rel_1/rtl
83	MAC address recognition was not correct (bytes swaped).	mohor	8092d 00h	/ethmac/tags/rel_1/rtl
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8092d 02h	/ethmac/tags/rel_1/rtl
80	Small fixes for external/internal DMA missmatches.	mohor	8096d 04h	/ethmac/tags/rel_1/rtl
79	RetryCntLatched was unused and removed from design	mohor	8096d 05h	/ethmac/tags/rel_1/rtl
78	WB_SEL_I was unused and removed from design	mohor	8096d 05h	/ethmac/tags/rel_1/rtl
77	Interrupts changed	mohor	8096d 05h	/ethmac/tags/rel_1/rtl
76	Interrupts changed in the top file	mohor	8096d 05h	/ethmac/tags/rel_1/rtl
75	r_Bro is used for accepting/denying frames	mohor	8096d 05h	/ethmac/tags/rel_1/rtl
74	Reset values are passed to registers through parameters	mohor	8096d 05h	/ethmac/tags/rel_1/rtl
73	Number of interrupts changed	mohor	8096d 05h	/ethmac/tags/rel_1/rtl
72	Retry is not activated when a Tx Underrun occured	mohor	8100d 09h	/ethmac/tags/rel_1/rtl

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[/] [ethmac/] [tags/] [rel_1/] [rtl/] - Rev 105

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