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[/] [ethmac/] [tags/] [rel_1/] [rtl/] - Rev 350

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Rev Log message Author Age Path
338 root 5493d 13h /ethmac/tags/rel_1/rtl
335 New directory structure. root 5550d 18h /ethmac/tags/rel_1/rtl
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7971d 11h /ethmac/tags/rel_1/rtl
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7971d 11h /ethmac/tags/rel_1/rtl
120 Unused files removed. mohor 7971d 13h /ethmac/tags/rel_1/rtl
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7971d 13h /ethmac/tags/rel_1/rtl
118 ShiftEnded synchronization changed. mohor 7975d 03h /ethmac/tags/rel_1/rtl
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7976d 12h /ethmac/tags/rel_1/rtl
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7977d 09h /ethmac/tags/rel_1/rtl
113 RxPointer bug fixed. mohor 7984d 01h /ethmac/tags/rel_1/rtl
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7984d 15h /ethmac/tags/rel_1/rtl
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7985d 04h /ethmac/tags/rel_1/rtl
110 m_wb_cyc_o signal released after every single transfer. mohor 7985d 07h /ethmac/tags/rel_1/rtl
109 Comment removed. mohor 7985d 08h /ethmac/tags/rel_1/rtl
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8052d 18h /ethmac/tags/rel_1/rtl
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8061d 19h /ethmac/tags/rel_1/rtl
104 FCS should not be included in NibbleMinFl. mohor 8063d 13h /ethmac/tags/rel_1/rtl
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8063d 14h /ethmac/tags/rel_1/rtl
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8063d 14h /ethmac/tags/rel_1/rtl
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8063d 14h /ethmac/tags/rel_1/rtl
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8063d 14h /ethmac/tags/rel_1/rtl
97 Small typo fixed. lampret 8087d 12h /ethmac/tags/rel_1/rtl
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8091d 12h /ethmac/tags/rel_1/rtl
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8091d 15h /ethmac/tags/rel_1/rtl
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8091d 15h /ethmac/tags/rel_1/rtl
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8096d 13h /ethmac/tags/rel_1/rtl
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8097d 15h /ethmac/tags/rel_1/rtl
91 Comments in Slovene language removed. mohor 8097d 15h /ethmac/tags/rel_1/rtl
90 casex changed with case, fifo reset changed. mohor 8097d 15h /ethmac/tags/rel_1/rtl
88 rx_fifo was not always cleared ok. Fixed. mohor 8107d 12h /ethmac/tags/rel_1/rtl

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