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[/] [ethmac/] [tags/] [rel_1/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

Rev	Log message	Author	Age	Path
80	Small fixes for external/internal DMA missmatches.	mohor	8096d 22h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8096d 23h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8107d 22h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8108d 03h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8108d 03h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8108d 18h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8110d 22h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8112d 06h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8114d 23h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8117d 01h	/ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v