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219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6557d 17h /ethmac/tags/rel_10/
218 Typo error fixed. (When using Bist) mohor 6557d 19h /ethmac/tags/rel_10/
217 Bist supported. mohor 6557d 19h /ethmac/tags/rel_10/
216 Bist signals added. mohor 6557d 19h /ethmac/tags/rel_10/
215 Bist supported. mohor 6557d 20h /ethmac/tags/rel_10/
214 Signals for WISHBONE B3 compliant interface added. mohor 6558d 16h /ethmac/tags/rel_10/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6558d 16h /ethmac/tags/rel_10/
212 Minor $display change. mohor 6558d 16h /ethmac/tags/rel_10/
211 Bist added. mohor 6558d 16h /ethmac/tags/rel_10/
210 BIST added. mohor 6558d 16h /ethmac/tags/rel_10/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6559d 20h /ethmac/tags/rel_10/
208 Virtual Silicon RAMs moved to lib directory tadej 6575d 13h /ethmac/tags/rel_10/
207 Virtual Silicon RAM support fixed tadej 6575d 14h /ethmac/tags/rel_10/
206 Virtual Silicon RAM added to the simulation. mohor 6575d 14h /ethmac/tags/rel_10/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6575d 14h /ethmac/tags/rel_10/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6575d 14h /ethmac/tags/rel_10/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6575d 14h /ethmac/tags/rel_10/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6578d 16h /ethmac/tags/rel_10/
201 Core size added to the document. mohor 6578d 16h /ethmac/tags/rel_10/
200 File with lower case checked in instead. mohor 6578d 16h /ethmac/tags/rel_10/

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