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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7842d 11h /ethmac/tags/rel_10/
235 rev 4. mohor 7843d 01h /ethmac/tags/rel_10/
234 Figure list assed to the revision 3. mohor 7843d 09h /ethmac/tags/rel_10/
233 Revision 0.3 released. Some figures added. mohor 7843d 10h /ethmac/tags/rel_10/
232 fpga define added. mohor 7848d 05h /ethmac/tags/rel_10/
231 Description of Core Modules added (figure). mohor 7850d 06h /ethmac/tags/rel_10/
229 case changed to casex. mohor 7854d 03h /ethmac/tags/rel_10/
227 Changed BIST scan signals. tadejm 7854d 06h /ethmac/tags/rel_10/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7854d 08h /ethmac/tags/rel_10/
225 Some minor changes. tadejm 7854d 08h /ethmac/tags/rel_10/
224 Signals for a wave window in Modelsim. tadejm 7854d 09h /ethmac/tags/rel_10/
223 Some code changed due to bug fixes. tadejm 7854d 09h /ethmac/tags/rel_10/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7858d 07h /ethmac/tags/rel_10/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7861d 08h /ethmac/tags/rel_10/
218 Typo error fixed. (When using Bist) mohor 7861d 10h /ethmac/tags/rel_10/
217 Bist supported. mohor 7861d 10h /ethmac/tags/rel_10/
216 Bist signals added. mohor 7861d 10h /ethmac/tags/rel_10/
215 Bist supported. mohor 7861d 11h /ethmac/tags/rel_10/
214 Signals for WISHBONE B3 compliant interface added. mohor 7862d 07h /ethmac/tags/rel_10/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7862d 07h /ethmac/tags/rel_10/
212 Minor $display change. mohor 7862d 07h /ethmac/tags/rel_10/
211 Bist added. mohor 7862d 07h /ethmac/tags/rel_10/
210 BIST added. mohor 7862d 07h /ethmac/tags/rel_10/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7863d 10h /ethmac/tags/rel_10/
208 Virtual Silicon RAMs moved to lib directory tadej 7879d 04h /ethmac/tags/rel_10/
207 Virtual Silicon RAM support fixed tadej 7879d 04h /ethmac/tags/rel_10/
206 Virtual Silicon RAM added to the simulation. mohor 7879d 04h /ethmac/tags/rel_10/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7879d 05h /ethmac/tags/rel_10/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7879d 05h /ethmac/tags/rel_10/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7879d 05h /ethmac/tags/rel_10/

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