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[/] [ethmac/] [tags/] [rel_10/] - Rev 240

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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7835d 09h /ethmac/tags/rel_10
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7835d 09h /ethmac/tags/rel_10
238 Defines fixed to use generic RAM by default. mohor 7847d 13h /ethmac/tags/rel_10
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7849d 19h /ethmac/tags/rel_10
235 rev 4. mohor 7850d 09h /ethmac/tags/rel_10
234 Figure list assed to the revision 3. mohor 7850d 17h /ethmac/tags/rel_10
233 Revision 0.3 released. Some figures added. mohor 7850d 18h /ethmac/tags/rel_10
232 fpga define added. mohor 7855d 13h /ethmac/tags/rel_10
231 Description of Core Modules added (figure). mohor 7857d 14h /ethmac/tags/rel_10
229 case changed to casex. mohor 7861d 11h /ethmac/tags/rel_10
227 Changed BIST scan signals. tadejm 7861d 14h /ethmac/tags/rel_10
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7861d 16h /ethmac/tags/rel_10
225 Some minor changes. tadejm 7861d 16h /ethmac/tags/rel_10
224 Signals for a wave window in Modelsim. tadejm 7861d 17h /ethmac/tags/rel_10
223 Some code changed due to bug fixes. tadejm 7861d 18h /ethmac/tags/rel_10
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7865d 15h /ethmac/tags/rel_10
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7868d 16h /ethmac/tags/rel_10
218 Typo error fixed. (When using Bist) mohor 7868d 18h /ethmac/tags/rel_10
217 Bist supported. mohor 7868d 18h /ethmac/tags/rel_10
216 Bist signals added. mohor 7868d 18h /ethmac/tags/rel_10

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