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Rev Log message Author Age Path
245 Rev 1.7. mohor 7839d 06h /ethmac/tags/rel_10
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7839d 08h /ethmac/tags/rel_10
243 Late collision is not reported any more. tadejm 7839d 14h /ethmac/tags/rel_10
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7840d 04h /ethmac/tags/rel_10
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7840d 04h /ethmac/tags/rel_10
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7840d 04h /ethmac/tags/rel_10
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7840d 04h /ethmac/tags/rel_10
238 Defines fixed to use generic RAM by default. mohor 7852d 08h /ethmac/tags/rel_10
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7854d 14h /ethmac/tags/rel_10
235 rev 4. mohor 7855d 04h /ethmac/tags/rel_10
234 Figure list assed to the revision 3. mohor 7855d 13h /ethmac/tags/rel_10
233 Revision 0.3 released. Some figures added. mohor 7855d 13h /ethmac/tags/rel_10
232 fpga define added. mohor 7860d 08h /ethmac/tags/rel_10
231 Description of Core Modules added (figure). mohor 7862d 09h /ethmac/tags/rel_10
229 case changed to casex. mohor 7866d 06h /ethmac/tags/rel_10
227 Changed BIST scan signals. tadejm 7866d 10h /ethmac/tags/rel_10
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7866d 11h /ethmac/tags/rel_10
225 Some minor changes. tadejm 7866d 11h /ethmac/tags/rel_10
224 Signals for a wave window in Modelsim. tadejm 7866d 13h /ethmac/tags/rel_10
223 Some code changed due to bug fixes. tadejm 7866d 13h /ethmac/tags/rel_10
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7870d 11h /ethmac/tags/rel_10
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7873d 11h /ethmac/tags/rel_10
218 Typo error fixed. (When using Bist) mohor 7873d 13h /ethmac/tags/rel_10
217 Bist supported. mohor 7873d 13h /ethmac/tags/rel_10
216 Bist signals added. mohor 7873d 13h /ethmac/tags/rel_10
215 Bist supported. mohor 7873d 14h /ethmac/tags/rel_10
214 Signals for WISHBONE B3 compliant interface added. mohor 7874d 10h /ethmac/tags/rel_10
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7874d 10h /ethmac/tags/rel_10
212 Minor $display change. mohor 7874d 10h /ethmac/tags/rel_10
211 Bist added. mohor 7874d 10h /ethmac/tags/rel_10

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