OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_10/] - Rev 363

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 4762d 02h /ethmac/tags/rel_10/
335 New directory structure. root 4819d 08h /ethmac/tags/rel_10/
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7125d 03h /ethmac/tags/rel_10/
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7125d 03h /ethmac/tags/rel_10/
245 Rev 1.7. mohor 7125d 21h /ethmac/tags/rel_10/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7125d 23h /ethmac/tags/rel_10/
243 Late collision is not reported any more. tadejm 7126d 05h /ethmac/tags/rel_10/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7126d 19h /ethmac/tags/rel_10/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7126d 19h /ethmac/tags/rel_10/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7126d 19h /ethmac/tags/rel_10/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7126d 19h /ethmac/tags/rel_10/
238 Defines fixed to use generic RAM by default. mohor 7138d 23h /ethmac/tags/rel_10/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7141d 05h /ethmac/tags/rel_10/
235 rev 4. mohor 7141d 19h /ethmac/tags/rel_10/
234 Figure list assed to the revision 3. mohor 7142d 04h /ethmac/tags/rel_10/
233 Revision 0.3 released. Some figures added. mohor 7142d 04h /ethmac/tags/rel_10/
232 fpga define added. mohor 7146d 23h /ethmac/tags/rel_10/
231 Description of Core Modules added (figure). mohor 7149d 00h /ethmac/tags/rel_10/
229 case changed to casex. mohor 7152d 21h /ethmac/tags/rel_10/
227 Changed BIST scan signals. tadejm 7153d 01h /ethmac/tags/rel_10/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7153d 02h /ethmac/tags/rel_10/
225 Some minor changes. tadejm 7153d 02h /ethmac/tags/rel_10/
224 Signals for a wave window in Modelsim. tadejm 7153d 04h /ethmac/tags/rel_10/
223 Some code changed due to bug fixes. tadejm 7153d 04h /ethmac/tags/rel_10/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7157d 02h /ethmac/tags/rel_10/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7160d 02h /ethmac/tags/rel_10/
218 Typo error fixed. (When using Bist) mohor 7160d 04h /ethmac/tags/rel_10/
217 Bist supported. mohor 7160d 04h /ethmac/tags/rel_10/
216 Bist signals added. mohor 7160d 04h /ethmac/tags/rel_10/
215 Bist supported. mohor 7160d 05h /ethmac/tags/rel_10/

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.