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[/] [ethmac/] [tags/] [rel_10/] [bench/] - Rev 182

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Rev Log message Author Age Path
182 Full duplex test improved. tadej 7915d 02h /ethmac/tags/rel_10/bench/
181 MIIM test look better. mohor 7915d 05h /ethmac/tags/rel_10/bench/
180 Bench outputs data to display every 128 bytes. mohor 7918d 01h /ethmac/tags/rel_10/bench/
179 Beautiful tests merget together mohor 7918d 02h /ethmac/tags/rel_10/bench/
178 Rearanged testcases mohor 7918d 02h /ethmac/tags/rel_10/bench/
177 Bug in MIIM fixed. mohor 7918d 05h /ethmac/tags/rel_10/bench/
170 Headers changed. mohor 7918d 08h /ethmac/tags/rel_10/bench/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7918d 08h /ethmac/tags/rel_10/bench/
158 Typo fixed. mohor 7923d 04h /ethmac/tags/rel_10/bench/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7925d 09h /ethmac/tags/rel_10/bench/
156 Valid testbench. mohor 7925d 09h /ethmac/tags/rel_10/bench/
155 Minor changes. mohor 7925d 09h /ethmac/tags/rel_10/bench/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7968d 03h /ethmac/tags/rel_10/bench/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7970d 04h /ethmac/tags/rel_10/bench/
117 Clock mrx_clk set to 2.5 MHz. mohor 7974d 06h /ethmac/tags/rel_10/bench/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7974d 06h /ethmac/tags/rel_10/bench/
108 Testbench supports unaligned accesses. mohor 8051d 10h /ethmac/tags/rel_10/bench/
107 TX_BUF_BASE changed. mohor 8051d 10h /ethmac/tags/rel_10/bench/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8096d 07h /ethmac/tags/rel_10/bench/
80 Small fixes for external/internal DMA missmatches. mohor 8117d 03h /ethmac/tags/rel_10/bench/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8127d 07h /ethmac/tags/rel_10/bench/
66 Testbench fixed, code simplified, unused signals removed. mohor 8127d 13h /ethmac/tags/rel_10/bench/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8129d 00h /ethmac/tags/rel_10/bench/
49 HASH0 and HASH1 register read/write added. mohor 8131d 00h /ethmac/tags/rel_10/bench/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8137d 06h /ethmac/tags/rel_10/bench/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8197d 08h /ethmac/tags/rel_10/bench/
23 Number of addresses (wb_adr_i) minimized. mohor 8247d 09h /ethmac/tags/rel_10/bench/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8247d 12h /ethmac/tags/rel_10/bench/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8272d 05h /ethmac/tags/rel_10/bench/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8312d 06h /ethmac/tags/rel_10/bench/

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