URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_10/] [rtl/] - Rev 241

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7841d 16h	/ethmac/tags/rel_10/rtl/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7841d 16h	/ethmac/tags/rel_10/rtl/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7841d 16h	/ethmac/tags/rel_10/rtl/
238	Defines fixed to use generic RAM by default.	mohor	7853d 20h	/ethmac/tags/rel_10/rtl/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7856d 01h	/ethmac/tags/rel_10/rtl/
232	fpga define added.	mohor	7861d 20h	/ethmac/tags/rel_10/rtl/
229	case changed to casex.	mohor	7867d 18h	/ethmac/tags/rel_10/rtl/
227	Changed BIST scan signals.	tadejm	7867d 21h	/ethmac/tags/rel_10/rtl/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7867d 23h	/ethmac/tags/rel_10/rtl/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7871d 22h	/ethmac/tags/rel_10/rtl/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7874d 23h	/ethmac/tags/rel_10/rtl/
218	Typo error fixed. (When using Bist)	mohor	7875d 01h	/ethmac/tags/rel_10/rtl/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7875d 22h	/ethmac/tags/rel_10/rtl/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7875d 22h	/ethmac/tags/rel_10/rtl/
212	Minor $display change.	mohor	7875d 22h	/ethmac/tags/rel_10/rtl/
211	Bist added.	mohor	7875d 22h	/ethmac/tags/rel_10/rtl/
210	BIST added.	mohor	7875d 22h	/ethmac/tags/rel_10/rtl/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7892d 20h	/ethmac/tags/rel_10/rtl/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7892d 20h	/ethmac/tags/rel_10/rtl/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7895d 21h	/ethmac/tags/rel_10/rtl/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7904d 00h	/ethmac/tags/rel_10/rtl/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7905d 00h	/ethmac/tags/rel_10/rtl/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7906d 01h	/ethmac/tags/rel_10/rtl/
165	HASH improvement needed.	mohor	7906d 04h	/ethmac/tags/rel_10/rtl/
164	Ethernet debug registers removed.	mohor	7906d 04h	/ethmac/tags/rel_10/rtl/
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7907d 01h	/ethmac/tags/rel_10/rtl/
160	error acknowledge cycle termination added to display.	mohor	7907d 01h	/ethmac/tags/rel_10/rtl/
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7907d 22h	/ethmac/tags/rel_10/rtl/
150	Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal was not used OK.	mohor	7911d 20h	/ethmac/tags/rel_10/rtl/
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7911d 20h	/ethmac/tags/rel_10/rtl/

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_10/] [rtl/] - Rev 241

Filtering Options